Final v0.3.3 validation evidence [M] · actual executed 7a0c93ff4d19b1892067711d884739d246432344; original CPU-WRF reference. Strict24 FAIL; raw full D6 FAIL; raw integrity FAIL-new-class; frozen integrity annex FAIL. 61 floor-limited rows; one real V10 miss. Rain and cirrus lifetime differences disclosed (L4/L6/L7). Strict24 · Full D6 · Raw integrity · Annex

W3_0115: all 73 hours, spatial deviation bands

All native stored cells, no masks; finite-first [M]. Blue: GPU-versus-original-CPU RMSE; orange: signed mean bias. Dark/light bands: spatial |error| p25–p75/p5–p95, not confidence intervals. Grey line: older-source GPU IC-pair empirical RMSE, not a CPU pair. Ratio row: deviation RMSE / pair RMSE where defined; reference lines1/2. The50% rule applies only to frozen D6 exceedance frames; zero denominators stay undefined. Dashed/off-scale arrow: unchanged D6 limit; hourly rain tau0 is undefined and its accumulated limit is informational.

Actual source-labelled comparison against original CPU-WRF; releasebe0 via explicit nativeBYTE628 bridge where measured source is7a. Frozen raw failures, frozen annex and manager Owner-ledger dispositions remain distinct; no source-execution relabel.

Frozen empirical spread: older-source RC 136c6e51c GPU IC pair (Tb2 vs Tb4), empirical spread only. References1/2 are guides; frozen gates remain separate. Pair spread is context, not fidelity truth, confidence interval or waiver. Original CPU-WRF supplies every blue deviation.

Summary n=1: cross-case sample SD is unavailable. Final summaries will show all cases and pointwise mean ± one sample SD per domain.

Plotted numerical data and source hashes